The present invention relates, generally, to systems for polishing or planarizing workpieces, such as semiconductor wafers. More particularly, it relates to an apparatus and method for electrochemical planarization of a wafer having a metallized surface.
The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. In addition, metallization, which generally refers to the materials, methods and processes of wiring together or interconnecting the component parts of an integrated circuit located on the surface of a wafer, is critical to the operation of a semiconductor device. Typically, the xe2x80x9cwiringxe2x80x9d of an integrated circuit involves etching trenches, or xe2x80x9cviasxe2x80x9d, in a planar dielectric (insulator) layer and filling the trenches with a metal.
In the past, the primary metallization material used in semiconductor fabrication was aluminum due to the leakage and adhesion problems experienced with the use of gold and the high contact resistance with silicon experienced with copper. Other metallization materials have included Ni, Ta, Ti, W, Ag, Cu/Al, TaN, TiN, CoWP, NiP and CoP. Over time, the semiconductor industry has slowly been moving to the use of copper for metallization due to the alloying and electromigration problems that are seen with aluminum. When copper is used as the filling, typically a barrier layer of another material is first deposited to line the trenches and vias to prevent the migration of copper into the dielectric layer. Barrier metals may be W, Ti, TiN, Ta, TaN, various alloys, and other refractory nitrides, which may be deposited by CVD, PFD, or electroless or electrolytic plating. To achieve good fill of the trenches and vias, extra metal is deposited in the process, such metal covering areas of the wafer above and outside the trenches and vias. After filling, planarization is typically conducted to remove the extra metal down to the dielectric surface. Planarization leaves the trenches and vias filled and results in a flat, polished surface.
Because of the high precision required in the production of integrated circuits, an extremely flat surface is generally needed on at least one side of the semiconductor wafer to ensure proper accuracy and performance of the microelectronic structures being created on the wafer surface. As the size of the integrated circuits continues to decrease and the density of microstructures on an integrated circuit increases, the need for precise wafer surfaces becomes more important. Therefore, between each processing step, it is usually necessary to polish or planarize the surface of the wafer to obtain the flattest surface possible.
For a discussion of chemical mechanical planarization (CMP) processes and apparatus, see, for example, Arai et al., U.S. Pat. No. 4,805,348, issued February 1989; Arai et al., U.S. Pat. No. 5,099,614, issued March 1992; Karlsrud et al., U.S. Pat. No. 5,329,732, issued July 1994; Karlsrud, U.S. Pat. No. 5,498,196, issued March 1996; and Karlsrud et al., U.S. Pat. No. 5,498,199, issued March 1996.
Typically, a CMP machine includes a wafer carrier configured to hold, rotate, and transport a wafer during the process of polishing or planarizing the wafer. During a planarization operation, a pressure applying element (e.g., a rigid plate, a bladder assembly, or the like), that may be integral to the wafer carrier, applies pressure such that the wafer engages a polishing surface with a desired amount of force. The carrier and the polishing surface are rotated, typically at different rotational velocities, to cause relative lateral motion between the polishing surface and the wafer and to promote uniform planarization.
In general, the polishing surface comprises a horizontal polishing pad that has an exposed abrasive surface of, for example, cerium oxide, aluminum oxide, fumed/precipitated silica or other particulate abrasives. Polishing pads can be formed of various materials, as is known in the art, and which are available commercially. Typically, the polishing pad may be blown polyurethane, such as the IC and GS series of polishing pads available from Rodel Products Corporation in Scottsdale, Ariz. The hardness and density of the polishing pad depend on the material that is to be polished.
While CMP tends to work very well for planarization if the correct slurry and process parameters are used, it may leave stresses in the worked workpiece, leading to subsequent cracking and shorting between metal layers. In addition, the semiconductor industry is increasing use of low k dielectrics, which tend to be fragile materials. CMP may result in shearing or crushing of these fragile layers. CMP also has a tendency to cause dishing into the center of wide metal features, such as trenches and vias, oxide erosion between metal features, and oxide loss of the dielectric.
Electrochemical planarization is an attractive alternative to CMP because it does not create stress in the workpiece and, consequently, does not reduce the integrity of the low k dielectric devices to the extent CMP may. Further, electrochemical planarization is less likely to cause dishing, oxide erosion and oxide loss of the dielectric layer.
Electrochemical planarization is based on electropolishing and electrochemical machining, that is, the removal of metal from a substrate by the combination of an electrochemical solution and electricity. FIG. 1 shows a conventional electroetching cell available in the prior art. A tank 2 holds a liquid electrolyte 4, an aqueous solution of a salt. Two electrodes, an anode 6 and a cathode 8, are wired to a voltage source, such as a battery 10. When the apparatus is electrified, metal atoms in the anode 6 are ionized by the electricity and go into the solution as ions. Depending on the chemistry of the metals and salt, the metal ions from anode 6 either plate the cathode 8, fall out as precipitate, or stay in solution.
When used for planarization of metal films on semiconductor wafers, conventional electrochemical planarization presents the disadvantage that the metal is not selectively removed from the wafer. FIG. 2 shows a dielectric layer 12 having trenches, or vias, and having a barrier metal layer 20 thereon. A metal layer 14 is deposited on the wafer over the barrier layer, filling the trenches. After being deposited on barrier layer 20, metal layer 14 may not be completely flat but, rather, may have areas of high topography 16 and low topography 18. With conventional electrochemical planarization, the metal layer is removed uniformly, so that the areas of high topography and low topography remain.
In planarization, however, xe2x80x9cstep-height reductionsxe2x80x9d is desired, that is, the selective removal of the metal layer at the high topography areas, followed by uniform removal of the metal layer. Step-height reduction should result in metal remaining only in the trenches and vias with a flat surface therein, as illustrated in FIG. 3.
Accordingly, there exists a need for an electrochemical planarization method and apparatus which accomplishes step-height reduction of metal layers on substrates, followed by uniform planarization of the metal layer.
These and other aspects of the present invention will become more apparent to those skilled in the art from the following non-limiting detailed description of preferred embodiments of the invention taken with reference to the accompanying figures.
In accordance with an exemplary embodiment of the present invention, an electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a platen, a conductive element disposed adjacent the platen and a polishing surface disposed adjacent the conductive element. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing surface while causing relative motion between the workpiece and the polishing surface. A voltage source is configured to effect an electric potential difference between the metallized surface of the workpiece and the conductive element. The apparatus further includes an electrolytic solution source and a solution application mechanism configured to supply an electrolytic solution from the electrolytic solution source to the polishing surface.
In accordance with a further embodiment of the present invention, a method of planarizing a metallized surface on a workpiece includes the steps of: providing a platen; providing a conductive element on the surface of the platen; providing a polishing surface on the surface of the conductive element; providing a workpiece carrier configured to carry a workpiece; pressing the workpiece against the polishing surface while causing relative motion between the workpiece and the polishing surface; establishing an electric potential difference between the metallized surface of workpiece and the conductive element; and supplying an electrolytic solution to the polishing surface.